Amplifier circuit



April 7, 1970 HISASHI EGUCHI ETAL 3,505,611

AMPLIFIER CIRCUIT Filed July 18, 1968 United States Patent 3,505,611 AMPLIFIER CIRCUIT Hisashi Eguchi and Hideo Matsuoka, Tokyo, Japan, assignors to Iwatsu Electric Co., Ltd., Tokyo, Japan Filed July 18, 1968, Ser. No. 745,777

Claims priority, application Japan, July 21, 1967,

Int. Cl. H03f 3/68 US. Cl. 330-30 3 Claims ABSTRACT OF THE DISCLOSURE The present invention relates to an amplifier circuit having large amplitude output and using NPN and PNP transistors for obtaining output wave signal having fast response.

Generally, in case of using PNP transistor in the amplifier circuit for obtaining large amplitude output signal, the characteristic feature of falling of the output signal is inferior in comparison with that of the rising of the output signal, on the contrary in case of using NPN transistor in the amplifier circuit, the characteristic feature of rising of the output signal is vice versa. To improve the above-mentioned drawbacks, a combined utilization of NPN and PNP transistors in the amplifier circuit was tried. In the above-mentioned combined utilization, the both collectors of the NPN and PNP transistor are directly connected. However, it is very diflicult to obtain the output signal having better frequency characteristic because of adding the excess collector capacity of the transistors to the loading capacity of the tran- Sistors respectively.

The principal object of the present invention is to provide an improved amplifier circuit eliminating the abovementioned drawbacks.

Other objects and features of the invention will more fully appear from the following description and the accompanying drawings and will be particularly pointed out in the claims.

FIG. 1 is a diagram illustrating an amplifier circuit embodying the present invention,

FIGS. 2A, 2B and 2C are wave form of the input signal, input signal of a NPN transistor and input signal of a PNP transistor of the amplifier circuit shown in FIG. 1, respectively,

FIG. 3 is a diagram illustrating the wave forms of the collector of the NPN transistor and PNP transistor of the amplifier circuit shown in FIG. 1.

Generally, the amplifier circuit of the present invention comprises PNP and NPN transistors, a diode inserted into a connection between collectors of the abovementioned two transistors. By the above-mentioned insertion of the diode, the falling character of the PNP transistor which is used as the A class amplifier can be compensated by a pulse signal impressed to the NPN transistor.

The detailed construction and function of the amplifier circuit of the invention is hereinafter illustrated with reference of the drawings. In an embodiment of the Patented Apr. 7, 1970 amplifier circuit of the invention shown in FIG. 1, a PNP transistor 1 forms A class amplifier. A compensation circuit which compensate a frequency character of an amplifier of the PNP transistor 1 comprises a NPN transistor 2 and a diode 3 which is inserted to a connection between a collector of the PNP transistor 1 and a collector of the NPN transistor 2. A collector capacity 4 of the PNP transistor 1, a collector capacity 5 of the NPN transistor 2, a resistance 6 of the PNP transistor 1, a resistance 7 of the NPN transistor 2 are arranged in the circuit as shown in FIG. 1.

When an input pulse as shown in FIG. 2A is impressed to an input terminal 8, an output pulse signal corresponding to the input pulse, for example an output pulse signal having volts of peak to peak, can be obtained at an output terminal 9 of the amplifier circuit shown in FIG. 1. When a base of the NPN transistor 2 is not impressed by any input signal, the transistor 2 is maintained at a cut-off condition or a condition being similar to the cut-01f condition. At the above-mentioned cut-off condition of the transistor 2, the diode 3 is maintained at an off condition, consequently the transistor 1 does not affect by the collector capacity 5 of the NPN transistor 2. On the other hand, as the PNP transistor 1 operates with large amplitude, the falling character of the transistor 1 becomes inferior one. However, when a positive pulse such as shown in FIG. 2B is impressed to the NPN transistor 2 at the time of the above-mentioned falling of the output of the PNP transistor 1, the collector potential of the NPN transistor 2 is fallen, and the condition of the diode 3 is changed to ON consequently the collector potential of the NPN transistor 2 is rapidly fallen, thereby the falling character of the output wave signal of the PNP transistor 1 can be improved. However, in the above-mentioned improvement, as a certain period defined by a time constant T: (collector capacity of the transistor 2) (resistance of the NPN transistor 2) is inevitable to recover the condition of the NPN transistor 2, there is certain restriction of the repetition rate of the amplified signal. Therefore, the above-mentioned amplifier circuit of the invention is effectively applied for the amplifier such as the unblanking amplifier of the oscilloscope wherein the input wave signal and the upper limit of the repetition rate are defined. Referring to FIGS. 1 and 2, when the NPN transistor 2 is not impressed by any input signal the output wave signal at the output terminal 9 is shown by a wave signal 10 in FIG. 3. As the output wave signal of the NPN transistor 2 is shown by a wave signal 11 in FIG. 3, the output wave signal at the output terminal 9 of the amplifier circuit having NPN and PNP transistors is improved as shown in a wave signal 12 in FIG. 3, where the working time of the diode 3 is represented by 13. As it is clearly shown in FIG. 3, the falling character of the output wave signal of the PNP transistor 1 is improved by operation of the NPN transistor 2, thereby the improved output wave signal 12 can be satisfactorily obtained.

In the above-mentioned embodiment, the PNP transistor 1 is used as a transistor having a function of A class amplifier and the NPN transistor 2 is used as a transistor having a function of switching operation, however a NPN transistor and a PNP transistor can be used on behalf of the above-mentioned PNP transistor 1 and NPN transistor 2 respectively to obtain the same operative function of the amplifier circuit shown in FIG. 1.

In the above-mentioned improved amplifier circuit, the influence of the collector capacity of the NPN transistor 2 affecting to the function of the PNP transistor 1 does not exceed over the magnitude of the reverse capacity of the diode 3. Consequently, by applying the improved amplifier circuit of the present invention, the frequency character of the amplifier circuit can be improved very much, further when a diode having smaller magnitude of the reverse capacity is used, the transistor having comparatively larger magnitude of the raverse capacity can be used. While, the transistor having small magnitude of the reverse capacity is preferably used as the transistor having a function of the high voltage transistor for switching of the conventional amplifier circuit, however the abovementioned-transistor is expensive.

While the invention has been described in conjunction with certain embodiments thereof, it is to be understood that various modifications and changes may be made without departing from the spirit and scope of the invention.

What is claimed is:

1. Amplifier circuit comprising, two parallel transistors of opposite polarity, one of said transistors comprising a class A transistor amplifier, a diode connected between the collectors of said transistors, output connections from said diode and said class A transistor amplifier, means for driving the class A transistor amplifier, means to impress on the other of said transistors a switching pulse to unblock it and superpose a negative output pulse on the output of said class A transistor amplifier to improve the trailing end of the output of said class A transistor amplifier and cause the class A transistor amplifier to have a square wave output of larger amplitude corresponding to a lesser amplitude input square wave to said class A transistor amplifier.

2. Amplifier circuit according to claim 1, in which said class A transistor amplifier comprises an PNP transistor and in which said other transistor comprises a NPN transistor.

3. Amplifier circuit according to claim 1, in which said class A transistor amplifier comprises an NPN transistor and the other transistor comprises a PNP transistor.

References Cited UNITED STATES PATENTS 3,333,113 7/1967 Cole et a1. 307241 X JOHN KOM'INSKI, Primary Examiner L. J. 'DAHL, Assistant Examiner US. Cl. X.R. 33017 Col. 1,

Patent No.

Inventor(s) Dated April 7, 1970 Hisashi Eguchi and Hideo Matsuoka line line line line line line line line line line line line line line line line 'line line line line line line line line line line line line delete delete insert delete delete delete delete after after delete delete delete delete delete delete It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

"Amplifier" and insert --An amplifier-; "of the invention comprises" and --having-;

"having" and insert --with--; "insert-" and insert --connected--; "ed into a connection";

"A" and insert --a--;

"class" insert -A--;

"NPN" insert --switching--;

"having a function of switching operation";

"impressed" and insert biased--; "trailing" and insert --decrease--; "thereby" and insert --whereby-; "trailing wave form" and insert --decreasing waveform--;

"rapid trailing" and insert --fall time--;

"having" insert --a--;

"of using" and insert --a--; "circuit" insert --is used--; "obtaining" insert -a--;

"of" first occurrence insert --the--; "of using" and insert --an--; "transistor" insert --is used-;

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"capacity" and insert --capacitance--; "capacity" and insert "capacitance";

FORM PO-1050 (10-69) USCOMM-DC GONG-P69 w u.s sovnunwr rnnmms or'nc: 1 an o-sia-su PAGE 2 Patent No.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Dated April 7, 1970 Inventor(s Col. 1,

Col. 2,

) Hisashi Eguchi and Hideo Matsuoka line line line line line line line line line line line line line line line line line line line line line line line line line line line delete after after delete after delete delete delete delete delete after delete delete delete delete after delete It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

"wave form of" and insert waveforms corresponding to--;

"signal'," insert --an--;

"and" insert --an--;

"wave forms" and insert --waveforms--; "transistors," insert --and-;

"serted into" and insert --in--;

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"the A" and insert -a-;

"class" insert --A transistor--; "impressed" and insert --applied-; "illustrated" and insert --described--;

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"inserted to" and insert --in--; "capacity" and insert --capacitance--; "capacity" and insert -capacitance--; "resistance" and insert --resistor--; "resistance" and insert --resist0r-; "input" insert -square wave--; "pulse" insert --l8--;

"shown in FIG. 2A is impressed"- and insert ---is applied;

PAGE 3 Patent No.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Dated April 7, 1970 1nventO1-(S) Hisashi Eguchi and Hideo Matsuoka line line line Col. 2,

line line line line line line line line line line line line line line line line It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

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"of" insert --voltage--;

"impressed by" and insert --receptive Of--;

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"falling" and insert --decay--; "becomes" insert --an-;

"pulse" insert --20-;

"such as shown in FIG. 2B is impressed"; and insert -is applied--;

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"class" insert --A--;

PAGE 4 Patent No.

Dated April 7, 1970 Inventor(s) Hisashi Eguchi and Hideo Matsuoka It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 2 line line line line line line Col. 3, line line line line line line line line line line line line after delete delete delete delete delete delete after delete delete delete after delete delete after delete delete delete "of" insert executing a;

"on behalf" and insert --in place--; "capacity" and insert --capacitance--; IItOII;

"over";

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Add the sheet of drawings as shown on the attached page,

[SEAL] Page 5 Signed and Sealed this twenty-fifth D a Of November 19 75 A Nest:

RUTH C. MASON .-l-rrsling Qlficer C. MARSHALL DANN ('nmmissiuncr 0/ Parents and Trudemarkx 

